PIC12F508/509 Rev. A Silicon/Data Sheet Errata

Module:
PIC12F509 debugging with ICD2 (PIC16F505-ICD silicon) – Invalid FSR Power-Up Initialization The FSR on the PIC16F505-ICD debugger silicon initializes to an invalid state.
When using the ICD to debug software with the PIC16F505-ICD, bit 5 in the FSR register must be manually cleared to ‘0’ prior to saving data in user RAM space.
The power-up default is ‘1’, which causes the device to Access Bank 1.
The power-up defaults are correct on the non-ICD version of the PIC12F509 devices.

2.1 Program Memory Organization
The PIC12F629/675 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) for the PIC12F629/675 devices is physically implemented.
Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).

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